This invention relates to a drive control apparatus which is applied to a disk storage system, such as a hard disk drive or an optical disk drive, has an interface function between a disk drive and a host system, and particularly controls data transfer.
A conventional external storage device, such as a hard disk drive (HDD), is generally incorporated in the body of a personal computer or provided outside a personal computer, for example. According to a command from the computer body (hereinafter, referred to as the host system), the storage device stores the data on a disk serving as a recording medium or reads the data from the disk and transfers it to the host system.
The HDD is roughly composed of a drive mechanism, a microcontroller, and a drive controller. The drive mechanism is roughly divided into a spindle mechanism that holds a disk in place and rotates it and a head driving mechanism that drives a head. The microcontroller is mainly made up of a microprocessor (CPU) and provides recording/reproducing control of data to a disk, head driving control, and disk rotating control.
In the HDD, the drive controller is also called a hard disk controller (HDC) and constitutes an interface between the disk drive and the host system and provides data transfer control (HDD data input/output control) between them. Receiving a command issued from the host system, the HDC executes a series of command processes and carries out data transfer control between the host system and the disk drive. In data transfer, the HDC uses a buffer memory (buffer RAM) to store the write data from the host system or the read data read from the disk into the buffer memory. In the write command processing, the HDC transfers the write data from the buffer memory to the disk. The write data is transferred as far as the head in the form of write current and is magnetically written on the disk. In the read command processing, the HDC transfers the read data from the buffer memory to the host system.
The command processing executed by the HDC starts with a command accepting process, followed by a series of processes, including a command recognition process, a BUSY setting process, a cache hit judging process, a data transfer process, a command address updating process, an interrupt generating process, and a BUSY clearing process. Hereinafter, the series of command processes, including the related operation of the CPU and buffer RAM, will be explained.
When the host system has issued a command (a read command or a write command), the HDC accepts the command and executes the process of recognizing the command. At this time, the HDC sets a BUSY flag in a drive status register 30 included in a control register group (see FIG. 3) in the HDC (BUSY set process), the BUSY flag indicating that the disk drive is in the BUSY state (during command execution). In the drive status register 30, for example, an error flag indicating that an error has occurred in the preceding command execution, a flag indicating a data transfer request, and a flag indicating that the disk drive is in the READY state (the command wait state) are set in addition to the BUSY flag.
The control register group is a register group which can be referred to by the host system and the CPU of the HDD and which includes an error register 31, a cylinder register 32, a head register 33, a sector count register 34, a sector number register 35, a command register 36, and a data register 37, in addition to the drive status register 30, as shown in FIG. 3, under the IDE (intelligent drive electronics) interface standard or the ATA interface standard. The error register 31 holds the contents of an error in the operation of the HDD. The cylinder register 32 holds the cylinder (track) number to be accessed on the disk. The head register 33 holds the head number selected in the HDD. The sector count register 34 holds the number of sectors transferred. The sector number register 35 holds the logical sector number obtained by address conversion in the command process. The command register 36 holds the command from the host system. The data register 37 holds the write data in the case of a write command and the read data in the case of a read command.
The HDC recognizes in a command recognition process whether the command is a write command, a read command, or a specific command other than a write and read commands. When it is a specific command other than a write and read commands, the HDC will pass control to the CPU. In the case of a read or write command, the HDC executes a cache hit judging process. In the cache hit judging process, it is judged whether the same address has been accessed. Specifically, in the case of a write command, it is judged whether or not an address to be accessed has been secured in the buffer RAM. If it has been secured (hit), the HDC stores the write data transferred from the host system at the address secured in the buffer RAM. In the case of a read command, it is judged whether or not the read data has been stored at the address to be accessed in the buffer RAM. If it has been stored (hit), the HDC reads the relevant read data from the buffer RAM and transfers it to the host system. Namely, the HDC transfers the read data directly from the buffer RAM to the host system without accessing the disk of the HDD. This eliminates the time required to access the disk and achieves high-speed data transfer.
After the CPU has prepared for data transfer, the HDC executes the data transfer process according to the data transfer instruction from the CPU. When the address to be accessed has not been hit in the cache hit judging process in the case of a write command, the HDC stores the write data in the buffer RAM after the CPU has prepared for reception of the write data (has secured an address in the buffer RAM). Additionally, when the address to be accessed has not been hit in the cache hit judging process in the case of a read command, the HDC stores into the buffer RAM the read data read from the disk under the control of the CPU. Furthermore, the HDC updates the command address, clears the BUSY flag after the CPU has issued a command end instruction, and goes to the command reception state. Namely, the HDC sets in the drive status register 30 a flag indicating that the disk drive is in the READY state.
As described above, after receiving a command from the host system, the HDC executes a series of commands one after another, and changes the various flags according to the contents of each of the command processes. The method of executing such a series of command processes serially, however, results in the complicated structure of the HDC because the method has a lot of condition flags and executes various operations according to the condition flags. This makes it very difficult to find defects in the processing steps in the stage of designing the HDC. Even if defects have been found after the HDC has been designed, it is impossible, for example, for a CPU to correct the defects and execute part of the command processing substitutively. To solve the problem, it is desirable that the series of command processes should be divided into a plurality of command processing steps and each of the common processing steps be executed independently. Furthermore, a method of enabling a CPU to refer to the operating state of each of the command processing steps is preferable. These methods, however, have not been realized yet.